# dofile_example.do

# DoFile notes (updated 050207)
#
# 1. Groups of nets cannot be made with "dangling wires" but they can still be routed!
#

unit mil

bestsave on C:\tmp\plonk_rev1.bst
status_file C:\tmp\plonk_rev1.sts

# Prerouting Commands
#
# max length of nets
circuit class All~SP~Nets (length 15000 100 (type actual))


# Fences. Dont overlap (merge) or butt as they will block paths.
#

# PS fence
area init_pt 10210 5938
area add_pt 10210 7716
area add_pt 10375 7716
area add_pt 10375 8412
area add_pt 4014 8412
area add_pt 4014 7342
area add_pt 4967 7342
area add_pt 4967 7076
area add_pt 7333 7076
area add_pt 7333 6661
area add_pt 7777 6661
area add_pt 7777 6493
area add_pt 8367 6493
area add_pt 8367 6203
area add_pt 8367 6121
area add_pt 8597 6121
area add_pt 8597 5926
area add_pt 10210 5926
area close_poly
fence digitized


# Analog fence
area init_pt 10414 7634
area add_pt 10414 6754
area add_pt 10530 6754
area add_pt 10530 4643
area add_pt 11350 4643
area add_pt 11350 4527
area add_pt 11933 4527
area add_pt 11933 4254
area add_pt 12415 4254
area add_pt 12415 7634
area close_poly
fence digitized

set soft_fence on


# track width & clearence
#
rule PCB (width 6)
rule PCB (clearance 6)


# Layer directions
#
direction TopLayer horizontal
select layer TopLayer
direction MidLayer1 vertical
select layer MidLayer1
direction MidLayer2 horizontal
select layer MidLayer2
direction BottomLayer vertical
select layer BottomLayer


# lAYER COSTS
#
#cost layer TopLayer high  (type length)
#cost layer MidLayer1 free  (type length)
#cost layer MidLayer2 free  (type length)
#cost layer BottomLayer high  (type length)


# Groupsets (of Classes) for routing
#
unsel all routing

#select  class  CS[0..6] DDATA[0..3] DQ[31..0] ERXD[0..3] ETXD[0..3] IRQ[1..6] PST[0..3] RA[12..1] UA[0..22] UD[0..15]
#define (group DIG1 (selected))
#unsel all routing
#
#select  class  PA[0..3]  PC[0..15]
#define (group DIG2 (selected))
#unsel all routing
#
#define (group_set grpset1 (add_group  DIG1))
#define (group_set grpset1 (add_group  DIG2))
#
#circuit group_set grpset1 (use_layer  MidLayer1 MidLayer2)


# Regions
#

# small BGA
area init_pt 5296 3902
area add_pt 5296 4703
area add_pt 4504 4703
area add_pt 4504 3902
area close_poly
define (region region1 (digitize (layer signal)))

# large BGA
area init_pt 7900 4300
area add_pt  9000 4300
area add_pt  9000 5400
area add_pt  7900 5400
area close_poly
define (region region2 (digitize (layer signal)))

# Power Supply
area init_pt 10210 5938
area add_pt 10210 7716
area add_pt 10375 7716
area add_pt 10375 8412
area add_pt 4014 8412
area add_pt 4014 7342
area add_pt 4967 7342
area add_pt 4967 7076
area add_pt 7333 7076
area add_pt 7333 6661
area add_pt 7777 6661
area add_pt 7777 6493
area add_pt 8367 6493
area add_pt 8367 6203
area add_pt 8367 6121
area add_pt 8597 6121
area add_pt 8597 5926
area add_pt 10210 5926
area close_poly
define (region region3 (digitize (layer signal)))


rule region region1 (clearance 5)
rule region region1 (width 5)
rule region region2 (clearance 5)
rule region region2 (width 5)
rule region region3 (clearance 8)
rule region region3 (width 25)

# Pre-routes
#
select area net 10410.3 6950.2 10410.3 6950.2 toggle
select area net 8800.9 5980.5 8800.9 5980.5 toggle
route 1 
unsel all routing

route 25