Chapter 2 of Microcomputer Hardware Design by Protopapas
Chapter Outline
- CPU Organization
- The External Interface
- Instruction Formats
- Addressing Modes
- Instruction Set
- CPU Timing
- Physical & Electrical Characteristics
View the class discussion outlines:
Central Processing Unit (Part 1)
Central Processing Unit (Part 2)
Using the uACE programming model, we implement the following code snippet:
ADDRESS INSTRUCTION MACHINE CODE E000 STS $E100 BF E1 00 ? LDAB $E101 F6 E1 01 ? PSHB 37 ? STS $E100 BF E1 00 ? LDAA $E101 B6 E1 01 ? LDAB #$01 C6 01 ? ABA 1B ? PULB 33 ? CBA 11Assume that the registers contain the following values before the execution of the above code:
ACC A = 00h ACC B = 00h IX = 0000h PC = E000h SP = 0070h Condition Code = 11000000bWhat are the values in the following memory locations?
(1 pt) E000 = ? (1 pt) E001 = ? (1 pt) E002 = ?What will be the final values of the following registers after the code snippet has been executed?
(3 pts) PC = ? (3 pts) SP = ? (3 pts) ACC A = ? (3 pts) ACC B = ? (3 pts) Condition Code = ?Illustrate the stack after PSHB is executed. Indicate the memory location(s), value(s) previous top of stack and new top of stack. (2 pts) Review Terms
ALU Instruction Register
Accumulator Interrupt Lines
Address Bus Little Endian
Arithmetic Shift Logic Shift
Based Index Addressing Machine Cycle
Based Mode Memory
Big Endian Microcoding
Buffer Register Microcomputer
Bus Control Lines Microprocessor
Byte One-Address Instruction
Control Instructions Op-Code
Control Unit Program
Data Bus Program Counter
Data Manipulation Instructions Register Direct Mode
Data Transfer Instructions Register Indirect Mode
Data Transfer Control Lines Registers
Direct Address Space Relative Indexed Addressing
Direct Addressing Mode Relative Mode
Firmware Set-up Time
Hardware Software
Hold Time Stack
Horizontal Microprogramming Stack Pointer
I/O controllers Status Register
Immediate Mode Vertical Microprogramming
Implied Mode Zero-Address Instruction
Indexed Mode Two's Complement
Instruction Cycle