Hi Holger:
Some people are having problems using Interlink with Quaderno and a Win98-PC based. I'm attaching you a Shareware utility that I've found very interestig (even if I still prefeer Interlink). File_id.diz for this utility follows: ZIP 2.12 is a tiny utility to transfer files between computers (desktop, notebook, or handheld) over a serial cable at high speed (115,200 bps).Faster than many similar programs; no memory-resident drivers; user configurable. Menu driven, or command line operation (works well in batch files). Can compare directories, back up changed files or entire directory trees. Requires IBM PC compatibles, "null modem" serial cable. Shareware. What about posting this Shareware on Quaderno's site?? I've dowloaded this about 2 weeks ago, and now I can't recall where or how did I find it (and I've been searching it again!!)
Best regards
...
Download the software: zipft

I've written a small program which sets user defined screen fonts for Quadeno V30's AT&T6300 graphics controller. I use it to use Cyrillic fonts on my Quaderno -- I live in Russia. May be it can be of some use for others -- I spend a few months to learn how to program Qudaerno's display controller. How can contribute it to Quaderno Infoworld?

Dear Sir,

As it seems there is not to much technical hardware information for the quaderno into your site, may I send you some technical destails about it.
This me be done in further mail, as I can collect sometimes hardware details.
May I suggest you to open a new "hard" page and put in it some links to several pages ,one for "each of the components" that are inside QuadernoXT-20.
(described below)

Here is what the "Quaderno General Service Manual" ref. 0234530M says (I have one paper form):

Quaderno XT-20 contains (1 line per component)

DOS Engine Chip PGS9101 Fujitsu ASIC
uPD70280 Nec main Cpu (refer to uPD70270/280 V41/V51 book)
M37410 Micon General Inoput Outputs chip Mitsubishi
PC87310 I/O
Video Chip 82C426 by Chips and Technology (Now Intel but cf Newtek)
DSP ref. ADSP2111 and ADSP 28msp02 memory by Analog Devices
Rom AM27C010
Rom D27C4001
Ram D42800
Serial Driver Converter MAX241 by Maxim

I join some files that are to be the
HArd Drive Specification:

- Picture 2520lap.jpg
- Text Description SCP2024.txt
- Tech document
- PC file IDE.zip that gives drive structure (cylinder and so on...)

Video Part:
CGA.txt about some register but not the full chip specification. I have the 82C426 in paper form but not html form!

CONNER PERIPHERALS

CP2024

Intelligent Disk Drive

Product Manual

Revision I

October 1990

3081 Zanker Rd.

San Jose, Ca. (408) 456-4500

Japan (81) 3-597-8321 Europe (49) 89-811-2097

NOTICE

Conner Peripherals make no warranty of any kind with regard

to this material, including, but not limited to, the implied

warranties of merchantability and fitness for a particular

purpose. Conner Peripherals shall not be liable for errors

contained herein or for incidental consequential damages

in connection with the furnishing, performance, or use

of this material.

Conner Peripherals, Inc. reserves the right to change, without

notification, the specifications contaioned in this manual.

Copyright Conner Peripherals, Inc. No part of this

publication may be reproduced or translated into any

language in any form without written permissiom of

Conner Peripherals, Inc.

IBM, PC/AT and PC/XT are registered trademarks of

International BUsiness Machines Corporation.

Table of Contents

1.0 Scope of Manual

2.0 Key Features

3.0 Specification Summary

3.1 Capacity

3.2 Physical Configuration

3.3 Performance

3.4 Read/Write

3.5 Power Requirements (Typical)

3.6 Physical Characteristics

4.0 Environmental Characteristics

4.1 Temperature

4.2 Humidity

4.3 Altitude (relative to sea level)

4.4 Reliability and Maintenance

4.5 Shock and Vibration

4.6 Magnetic Field

4.7 Acoustic Noise

4.8 Safety Standards

5.0 Functional Description

5.1 Read/Write and Control Electronics

5.2 Drive Mechanism

5.3 Air Filtration System

5.4 Head Positioning Mechanism

5.5 Read/Write Heads and Disks

5.6 Error Correction

5.7 Customer Options

6.0 Interface Connector

6.1 Diagnostic Routines

7.0 Recommended Mounting Configuration

8.0 Electrical Description

8.1 Signal Levels

8.2 Pin Descriptions

1.0 Introduction

The CP2024 is a high performance 2.5 inch low-profile (.69")

21.4 megabyte (formatted) disk drives with average seek time

not to exceed 23ms which is designed to operate on an

IBM PC/XT & PC/AT or equivalent computer. The drives

feature a low 5V power requirement and high shock resistance,

enabling battery operation in portable environments.

In order for the CP2024 to communicate with the host system,

it is necessary for the system to contain a IDE interface.

(The IDE interface contains the address decode logic.)

This interface may be either built into the system, or may

be placed on a 8 bit or 16 bit I/O card, which can be placed

into any open I/O slot within a IBM XT or AT type system.

1.1 Scope

This specification describes the key features, specification

summary, physical characteristics, environmental characteristics,

functional description, electrical interface, recommended

mounting configuration, and error reporting for the Conner

Peripherals model CP2024.

2.0 Key Features

o 2.5" Form factor

o Single 5 Volt supply

o Low power requirements

o 6.0 oz

o High performance rotary voice coil actuator with

embedded servo system.

o Single connector for power & interface

o Run length limited code (1/7 or 2/7)

o High shock resistance

o Internal air filtration system

o Sealed HDA

o Automatic actuator latch against inner stop upon power down

o Microprocessor-controlled diagnostic routines that are

automatically executed at start-up

o Automatic error correction and retries

o Block size 512 bytes

o PC XT/AT interface (interface selectable)

o 1:1 Interleave

o Look Ahead Read Capability

o 8K Buffer

o Master/Slave option

3.0 Specification Summary

3.1 Capacity

21.4 Mbytes Formatted

3.2 Physical Configuration

Actuator Type Rotory Voice-coil

Number of Disks 1

Number of Surfaces 2

Number of Heads 2

Servo Embedded

Tracks per Surface 653

Track Density 1700 TPI

Formatted Track (Bytes) 16,384

Bytes per Block 512

Blocks per Drive 41,856

Sectors per Track 32

3.3 Performance

Seek Times

Track to Track 8.0 ms

Average 23.0 ms

Maximum 40.0

Rotation Speed 3433 RPM

Data Transfer Rate 1.25 Mbytes per/sec

Start Time

Typical 7 sec

Maximum 15 sec

Stop Time

Typical 1.5 sec

Maximum 3.0 sec

Interleave 1:1

Buffer Size 8K

The timing is measured through the interface with the

drive operating at nominal DC input voltages. The

timing also assumes that:

o BIOS and PC system hardware dependency

have been subtracted from timing measurements.

o The drive is operated using its native drive

parameters.

The average seek time is determined by averaging the

seek time for a minimum of 1000 seeks of random

length over the surface of the disk. These numbers

assume spin recovery is not invoked. If spin recovery

is invoked, the maximum time could be up to 40 seconds.

Briefly removing power can lead to spin recovery being

invoked.

3.4 Read/Write

Interface XT/AT

Recording Method 2/7 RLL

Recording Density 33,233

Flux Density 22,155

3.5 Power Requirements: +5V DC

R/W 585 ma 3.0 W

Seek 585 ma 3.0 W

Idle 267 ma 1.5 W

Standby 74 ma .45 W

Sleep 58 ma .25 W

Spin-up 832 ma N/A

Read/Write/Seek Mode: occurs when data is being read

from or written to the disk, or when the actuator mechanism

is in motion.

Idle Mode: occurs when the drive is not reading, writing or

seeking. The motor is up to speed and DRIVE READY condition

exists. Actuator is residing on last accessed track.

Standby Mode: occurs when the motor is stopped and actuator

is parked. STANDBY MODE will occur after a programmable

time-out since last host access occurs. The drive will leave

STANDBY MODE upon receipt of a command which requires disk

access or upon receipt of a spin up command.

Sleep Mode: occurs when the drive is issued a command of E6h.

The drive motor is stopped and all electronics are put into

a reduced current mode. The 12 VCC power produced by U2 is

cut off, thus eliminating power to the pre-amp IC. A host

reset is required to exit sleep mode.

Maximum noise allowed (DC to 1 MHZ, with equivalent

resistive load): +5V DC: 2%.

4.0 Physical Characteristics

.69" x 2.75" x 4.00"

5.0 Environmental Characteristics

Temperature

Operating 5 deg. C to 55 deg. C

Non-operating -40 deg.C to 60 deg. C

Thermal Gradient 20 deg. C per Hr. Max

Humidity

Operating 8% to 80% Non-condensing

Non-operating 8% to 80% Non-condensing

Max Wet Bulb 26 deg. C/hour

Altitude (relative to sea level)

Operating -200 to 10,000 Ft.

Non-operating 40,000 Ft.

5.1 Reliability and Maintenance

MTBF 100,000 Hours (POH)

MTTR 10 min typical

Maint. None

5.2 Shock

Non-operating 100 Gs

Operating 10 Gs

5.3 Magnetic Field

The disk drive will meet its specified performance while

operating in the presence of an externally produced magnetic

field under the following conditions:

Frequency Field Intensity

0 to 1.5 Mhz 6 gauss Max

1.5 Mhz 1 gauss Max

5.4 Acoustic Sound Emission

Power - TBD

Pressure - 34 dBa at 1 meter

5.5 Safety Standards

The CP2024 disk drive is designed to comply with relevant

product safety standards such as:

o UL 478, 5th edition, Standard for Safety of Information

Processing and Business Equipment, and

UL 1950, Standard for Safety of Information Technology

Equipment

o CSA 22.2 #154, Data Processing Equipment and

CSA 22.2 #220, Information Processing and Business Equipment.

o IEC 435 Safety Requirements for Data Processing Equipment,

IEC 380, Safety of Electrically Energized Office Machines, and

IEC 950, Safety of Information Technology Equipment Including

Electrical Business Equipment.

o VDE 0805 Equivalent to IEC 435,

VDE 0805 TIEL 100, Equivalent to IEC 950, and

VDE 0806, Equivalent to IEC 380.

6.0 Functional Description

The CP2024 contains all necessary mechanical and electronic parts to

interpret control signals, position the recording heads over the

desired track, read and write data, and provide a contaminant free

environment for the heads and disks.

6.1 Read/Write and Control Electronics

One integrated circuit is mounted within the sealed enclosure in

close proximity to the read/write heads. Its function is to provide

one of two head selection, read preamplification, and write data

circuitry.

The single microprocessor controlled circuit card provides the

remaining electronic functions which include:

o Read/Write Circuitry

o Rotary Actuator Control

o Interface Control

o Spin Speed Control

o Dynamic Braking

o Power Management

At power down or the start of STANDBY MODE the heads are automatically

retracted to the inner diameter of the disk and are latched and parked

on a landing zone that is inside the data tracks.

6.2 Drive Mechanism

A brushless DC direct drive motor rotates the spindle at 3433 RPM.

The motor/spindle assembly is balanced to provide minimal mechanical

runout to the disks and to reduce vibration of the HDA. A dynamic brake

is used to provide a fast stop to the spindle motor when power is removed,

or upon initiation of STANDBY MODE.

6.3 Air Filtration System

Within the sealed enclosure, a .3 micron filter provides a clean

environment to the heads and disks.

6.4 Head Positioning Mechanism

The read/write heads are supported by a mechanism coupled to the

voice coil actuator.

6.5 Read/Write Heads and Disks

Data is recorded on one 65mm diameter disk through two miniature

thin film heads.

6.6 Error Correction

The CP2024 performs internal error correction. The error correction

polynomial is capable of correcting one error burst with a maximum

of 8 bits per 512 byte block. The following polynomial is used:

Forward: P(X) = (X32+X28+X26+X19+X17+X10+X6+X2+1)

6.7 Customer Options

The CP2024 can operate either as a master (C Drive) or a slave

(D Drive) depending on the state of jumpers and the setting of Bit 4

in the feature byte. When the feature Byte, bit 4, is active (1),

and E2 is jumpered, the drive will assume the role of master

(for example: feature byte = 1Ø). The slave (D drive) must have

the E1/E2 jumper in the storage position.

7.0 Interface Connector

The CP2024 has a 44 pin right angle interface/power connector

mounted on the PCB. The recommended mating connector part number

from Elco Corporation for the Flat Ribbon type is

20-8394-2050-02101S; and for the Solder Tail type it is Vertical

PCB 20-8390-2050-00101. The maximum cable length is two feet.

7.1 Diagnostic Routines

The microprocessor performs diagnostics upon application of power.

If an error is detected, the CP2024 will not come ready.

8.0 Recommended Mounting Configuration

The CP2024 drive is designed to be used in applications where

the unit may experience shock and vibrations at greater levels

than larger and heavier disk drives.

The design features which allow greater shock tolerance are the

use of rugged heads and media, a dedicated landing zone, closed

loop servo positioning and specially designed motor and actuator

assemblies.

Four (8) mounting points are provided to the customer. The drive

is mounted from the bottom using 4-40 screws 0.19 inch max insertion.

Side mounting is also available using 2.5mm x .5 x .19 screws.

The system integrator should allow ventilation to the drive to ensure

reliable drive operation over the operating temperature range. The

drive may be mounted in any attitude.

For additional vibration isolation, an external suspension system may

be used.

9.0 Electrical Description

9.1 Signal Levels

All signal levels are TTL compatible. A logic "1" is >2.0 Volts.

A logic "0" is from 0.00 Volts to .70 Volts. The drive capability

of each of the inbound signals is described below.

9.2 Pin Descriptions

Signal Name Dir Pin Description

-RESET 0 1 Reset signal from the Host system which

is active low during power up and inactive

thereafter.

GND 0 2, 19 Ground between the drive and

22, 24 Host.

26, 30

40, 43

+DATA 0-15 I/O 3-18 16 bit bi-directional data bus between

the host and the drive. In AT mode, the

lower 8 bits, HD0-HD7, are used for register

& ECC access. All 16 bits are used for data

transfers. In XT mode, only the lower 8

bits are used. These are tri-state lines

with 10mA drive capability.

KEY N/C 20 An unused pin clipped on the drive and

plugged on the cable. Used to guarantee

correct orientation of the cable.

RESERVED 0 21, 28 Reserved

-IOW 0 23 Write strobe, the rising edge of which

clocks data from the host data bus into

a register or the data register of the drive.

-IOR 0 25 Read strobe, which when low enables

data from a register or the data register

of the drive onto the host data bus. The

rising edge of IOR latches data from the

drive at the host.

-DACK 0 27 DMA hand shake signal used to select

drive data register (XT only).

+DRQ I 29 DMA hand shake signal used to request

data byte transfer (XT only).

+IRQ I 31 Interrupt to the Host system. In AT mode

this signal is enabled only when the drive

is selected, and the host activates the

-IEN bit in the Digital Output Register.

When the -IEN bit is inactive, or the

drive is not selected, this output in a

high impedance state, regardless of the

state of the IRQ bit. The interrupt is

set when the IRQ bit is set by the dive CPU.

IRQ is reset to zero by a Host read of the

Status register or a write to the command

register. In XT mode, this signal is

enabled when the IRQ enable bit is set

and the drive has completion status

available for the host. This signal is a

tristate line with 10mA drive capacity.

-I016 I 32 Indication to the Host system that the 16

bit data register has been addressed and

that the drive is prepared to send or

receive a 16 bit data word. This line is

tri-state line with 20 mA drive capacity.

(AT mode only).

-PDIAG I/O 34 At POR -PDIAG will be activated by the

slave within 1 ms. If the master doesn't

see -PDIAG active after 4 ms it will

assume no slave is present. -PDIAG will

remain active until the slave is ready to go

not busy or 14.0 seconds on a power on

reset. The master will wait 14.5 seconds

or until the slave deactivates -PDIAG on

power on reset before it goes not busy.

The salve will de-activate -PDIAG and go

not busy, if it is not ready after the 14.0

seconds. Neither drive will set ready or

seek complete until they have reached full

spin speed and are ready to read/write.

+A0,A1,A2 0 35,33, Bit binary coded address used to select

36 the individual registers in the drive.

-CS0 0 37 Chip select decoded from the host

address bus. Used to select some of the

Host accessible registers.

Note: This signal should be disabled by

the Host when data transfers are in

progress.

-CS1 0 38 Chip select decoded from the Host

address bus. Used to select three of the

registers in the Task File. AT mode only.

-ACTIVE I 39 Signal from the drive used to drive an

active LED whenever the disk is being

accessed.

+5V (Logic) 0 41 5 volt +/- 5% supply to drive circuitry.

+5V (Motor) 0 42 5 volt +/- 5% supply to drive motors.

-XT/AT 0 44 Interface mode select. This signal is

sampled on power up and will select XT or

AT operating mode as requested by the

Host.

_

IBM Color Graphics Adapter (CGA)

The original CGA was built with discrete logic around an MC6845 display

controller.

On the original CGA and some clones accessing the video memory during the

active display time caused the display controller to miss some pixels (seen as

"snow"), which is the reason many programs only accesses video memory during

vertical or horizontal retrace. This is fixed in some clones and in EGA/VGA

adapters.

Basic features:

80x25 text modes in 16colors

320x200 4color graphics modes

640x200 2 color graphics mode

TTL video interface (Red, Green, Blue and Intensity)

16KB Video RAM and 2KB ROM for 8x8 font.

Clones:

Commodore AGA:

Combines CGA, MDA, Hercules and Plantronics support in one chip.

Chips & Tech 82c425:

Supports both CRT and LCD displays. Greyscale on LCD, supports two softfonts

(up to 8x16 pixels) allowing 512 characters on screen. No Snow.

Chips & Tech 82c426:

Same as 82c425, but also supports Sleep mode, AT&T 400 line Graphics Mode,

Color LCDs and upto 32KB video memory.

3D4h (W): Index register.

The value written to this register selects which of the data

registers will be accessed at 3D5h.

3D4h index 00h (W): Horizontal Total Register

Bit 0-7 Number of characters (-1) in a scan line incl. retrace.

Note: this register is Read/Write on the CT82c425/6.

3D4h index 01h (W): Horizontal Displayed Register

Bit 0-7 Number of characters (-1) displayed during a scan line.

Note: this register is Read/Write on the CT82c425/6.

3D4h index 02h (W): Horizontal Sync Position Register

Bit 0-7 Number of characters displayed before Horizontal Sync pulse starts.

Note: this register is Read/Write on the CT82c425/6.

3D4h index 03h (W): Horizontal Sync Width Register

Bit 0-7 Number of character clocks during a Horizontal Sync pulse.

Note: this register is ignored on the CT82c425/6.

3D4h index 04h (W): Vertical Total Register

Bit 0-6 Number of character rows in a frame. This is adjusted by the number

of scanlines in a character (index 9) and the Vertical Adjust (index

5).

Note: this register is Read/Write on the CT82c425/6.

3D4h index 05h (W): Vertical Total Adjust Register

Bit 0-3 Number of scanlines added to the Vertical Total time.

Note: this register is Read/Write on the CT82c425/6.

3D4h index 06h (W): Vertical Displayed Register

Bit 0-6 Number of character rows displayed per frame.

Note: this register is Read/Write on the CT82c425/6.

3D4h index 07h (W): Vertical SyncPosition Register

Bit 0-6 Number of character rows displayed before the Vertical Sync pulse

starts.

Note: this register is Read/Write on the CT82c425/6.

3D4h index 08h (W): Interlace Mode Register

Note: this register is ignored on the CT82c425/6 and F8680.

3D4h index 09h (W): Maximum Scan Line Register

Bit 0-3 Number of scanlines (-1) in a character row.

Note: this register is Read/Write on the CT82c425/6.

3D4h index 0Ah (W): Cursor Start Register

Bit 0-4 The scanline (starting from 0) within the character where the

cursor starts.

5-6 Cursor Attributes:

0,2: Cursor is blinking at the blink rate.

1: Cursor is turned off.

3: Cursor is blinking at half the blink rate.

The default blink rate is 1/16 of the frame rate (8 frames on, 8

off).

Note: this register is Read/Write on the CT82c425/6.

3D4h index 0Bh (W): Cursor End Register

Bit 0-4 The scanline (starting from 0) within the character where the

cursor ends. If the start position (index 0Ah) is larger than this

value, no cursor is shown.

Note: this register is Read/Write on the CT82c425/6.

3D4h index 0Ch (W): Start Address High Register

Bit 0-5 The upper 6 bits of the address of the start of the display.

The lower 8 bits are in index 0Dh.

Note: this register is Read/Write on the CT82c425/6.

3D4h index 0Dh (W): Start Address Low Register

Bit 0-7 The lower 8 bits of the address of the start of the display.

The upper 6 bits are in index 0Ch.

Note: this register is Read/Write on the CT82c425/6.

3D4h index 0Eh (W): Cursor Location High Register

Bit 0-5 The upper 6 bits of the address of the start of the cursor.

The lower 8 bits are in index 0Fh.

Note: this register is Read/Write on the CT82c425/6.

3D4h index 0Fh (W): Cursor Location Low Register

Bit 0-7 The lower 8 bits of the address of the start of the cursor.

The upper 6 bits are in index 0Eh.

Note: this register is Read/Write on the CT82c425/6.

3D4h index 10h (W): Light Pen High Register

Bit 0-5 The upper 6 bits of the latched address of the lightpen strobe.

The lower 8 bits are in index 11h.

Note: this register is Read/Write on the CT82c425/6.

3D4h index 11h (W): Light Pen Low Register

Bit 0-7 The lower 8 bits of the latched address of the lightpen strobe.

The upper 6 bits are in index 10h.

Note: this register is Read/Write on the CT82c425/6.

3D4h index D3h (R/W): Grey-level Control Register #1 (CT82c426 only)

bit 0-7 GC10-17. Parameter for the Monochrome Alternate GrayScale algorithm.

Recommended value is 43h. Bit 3 should be 0.

3D4h index D4h (R/W): Grey-level Control Register #2 (CT82c426 only)

bit 0-7 GC20-27. Parameter for the Monochrome Alternate GrayScale algorithm.

Recommended value is E6h. Bits 3 and 7 should be 0.

3D4h index D5h (R/W): General-Purpose Register (CT82c426 only)

bit 0 General Purpose I/O bit 1. Data to/from the GPIO1 pin.

1 General Purpose I/O 1 Three State Control.

If set the GPIO1 pin is three-stated and can be used as an input.

If clear the pin is an output.

2 General Purpose I/O 1 Mux Control.

If set the GPIO1 pin is fed with the data in bit 0, if clear with the

Display Enable bit (3DAh bit 0).

4 General Purpose I/O bit 2. Data to/from the GPIO2 pin.

5 General Purpose I/O 2 Three State Control.

If set the GPIO2 pin is three-stated and can be used as an input.

If clear the pin is an output.

6 General Purpose I/O 2 Mux Control.

If set the GPIO2 pin is fed with the data in bit 4, if clear with the

ROMCS/ signal

3D4h index D6h (R/W): Sleep Register (CT82c426 only)

bit 0 Sleep Mode Software Enable. If a 1 is written to this bit, the 82c426

enters sleep mode when the current display fetch completes.

In sleep mode video memory can not be accessed and the SLEEP pin is

driven high. If a 0 is written normal operation resumes.

1 (R) Sleep Mode Output. Reflects the state of the SLEEP output pin.

1 if the 82c426 is in sleep mode or if the Video Enable bit is 0.

3D4h index D7h (R/W): Panel Size Register (CT82c426 only)

bit 0-7 Size of the upper panel (if a two panel system) in scanlines (-1).

3D4h index D8h (R/W): Panel Configuration Register (CT82c426 only)

bit 0-2 LCD Mode. Panel type:

0: Single Panel, Single Drive

1: Dual-Panel, Single Drive

2: Dual-Panel, Dual Drive

3: Single Panel, 12bit color

4: Single Panel, 4bit color

3 Alternate FLM. If clear the FLM (First Line Marker) is generated as

in the 82c425: Rising before the LP of the first line and falling

after it. If set FLM rises when the last LP of the frame falls, and

falls with the falling edge of the first LP of the frame.

4 Scan-Doubling Enabled. If set and bit 5 is 0, the scanlines are

doubled.

5 AT&T Mode Enabled. If set the AT&T Mode register (3DEh) is enabled.

If clear the AT&T register is inaccessible.

6-7 Memory Configuration 0-1.

0: 3 8Kx8 SRAM or 2 8Kx8 SRAM and 1 8Kx8 ROM.

1: 1 32Kx8 SRAM

2: 1 16Kx8 SRAM and 1 8Kx8 SRAM/ROM

3: 1 32Kx8 SRAM and 1 8Kx8 SRAM/ROM

3D4h index D9h (R/W): AC Control Register (CT82c425/6 only)

Bit 0-4 The number of LCD Latch Pulses (-1) for which the AC signal is on

and off (50% duty cycle)

7 If set the programmable AC signal is enabled. If clear, the AC signal

remains ON for one frame and OFF for the next.

3D4h index DAh (R/W): Threshold Register (CT82c425/6 only)

Bit 0-3 Threshold Value.

4 Saturation. If set the shifts in fore- and background colors by

SMARTMAP is limited to the saturation points, if clear the

colormapping will be modulo 16

5 Four Grey Scale Bit. If set 4 grey scales is selected, if clear 8

grey scales is selected for text modes.

6 (82c426 only) Alternate Graylevel Algorithm.

3D4h index DBh (R/W): Shift Parameter Register (CT82c425/6 only)

Bit 0-3 Foreground Shift. The amount of shift for ForeGround colors in the

text grey scale scheme.

4-7 Background Shift.

3D4h index DCh (R/W): Horizontal Sync Width Register (CT82c425/6 only)

Bit 0-7 Number of Dot clocks in the HSYNC pulse.

3D4h index DDh (R/W): Vertical Sync Width Register (CT82c425/6 only)

Bit 0-3 Vertical Sync Width in scanlines (-1).

4-7 Blink rate of characters. The character will be on for (value+1)

frames and off for the same number of frames.

The cursor blink rate is twice the character blink rate.

3D4h index DEh (R/W): Shift Parameter Register (CT82c425/6 only)

Bit 0-4 (82c425 only) ECLK. The number of output clock pulses (-1) per pulse

of the ENABLE CLOCK for the LCD panel

0-3 (82c426 only) (R) Silicon Revision.

5 CLK SEL. 0 selects the CLK1 input as the master clock source, 1

selects the CLK2 input.

6-7 CCLK DIV 0-1. Determines the panel shift clock (PCLK) and pixel

clock.

Value: Pixel freq: PCLK (LCD):

0 CLKIN CLKIN/4

1 CLKIN/2 CLKIN/8

2 CLKIN/3 CLKIN/12

3 CLKIN/4 CLKIN/16

3D4h index DFh (R/W): Function Control Register (CT82c425/6 only)

Bit 0 Decode Enable. If clear all accesses to the video memory and the 3Dxh

registers will be disabled, except for writes to this bit.

When set the memory and registers are accessible.

1 Font Enable. If set the font memory can be accessed at B8000h-B9FFFh.

If clear the font memory is inaccessible.

2 Font Select. If set the font at B9000h is selected, if clear the font

at B8000h is the default.

3 If set the CRT output is selected, if clear the LCD.

4 (LCD only) Status Control. Controls the behavior of the Display

Enable bit (3DAh bit 0) and Vertical Sync bit (3DAh bit 3).

If clear, the Display Enable bit toggles every 16 character clocks,

and the Vertical Sync bit is active during the first scanline.

If set the Display Enable bit is active during the first 16 character

clocks of each scanline, and from row 22 till the end of the panel in

text modes (row 85 in graphics modes). The Vertical Sync bit is

active through all scanlines of row 24 in textmodes (row 93 - 96 incl

in graphics modes).

5 (LCD only) Enable Control.

6 If set bit 3 of the attribute byte selects the font, rather than

intensity.

7 If set the video outputs are inverted.

3D8h (W): Mode Control register

bit 0 80x25 Alpha mode if set, 40x25 else

1 Graphics mode if set, alpha else.

2 BW mode if set, color else

3 Video Enable. Enable video signal if set

4 640x200 Graphics mode if set, 320x200 else

5 if set bit 7 of the attribute controls background, else blink

Note: this register is Read/Write on the CT82c425/6.

3D9h (W): Color Select register

The function of this register depends on the active mode.

Text modes: 320x200 modes: 640x200 mode:

Bit 0 Blue border Blue background Blue ForeGround

1 Green border Green background Green ForeGround

2 Red border Red background Red ForeGround

3 Bright border Bright background Bright ForeGround

4 Backgr. color Alt. intens. colors Alt. intens colors

5 No func. Selects palette

Palette 0 is Green, red and brown,

Palette 1 is Cyan, magenta and white.

Note: this register is Read/Write on the CT82c425/6.

3DAh (R): Status register

bit 0 Display Enable. If set Horizontal or Vertical Retrace is active and

the video memory may be accessed by the PC.

1 Lightpen trigger has occurred if set

2 Lightpen switch is off if set

3 Vertical Sync. Vertical retrace active if set.

Video RAM can be accessed for the next 1.25 ms.

Note: The CT82c425/6 modifies bits 0 and 3 for LCD panels. See 3D4h index DFh.

3DBh (R/W) Clear Light Pen Strobe

Reading or writing this register clears the lightpen strobe. This can happen

before or after the lightpen position is read from 3D4h index 10h-11h.

3DCh (R/W): Set Light Pen Strobe

Reading or writing this register sets the lightpen strobe, causing the

lightpen position to be latched to 3D4h index 10h-11h.

The strobe must be cleared by accessing register 3DBh.

3DDh (W): (AGA - Plantronics)

bit 4 Set for 320x200 16color mode, clear for all other (16color?) modes

5 Set for 640x200 4color mode, clear for all other (4color?) modes

6 If set plane0 is at BC000h-BFFFFh and plane1 at B8000h-BBFFFh,

if clear plane0 is at B8000h-BBFFFh and plane1 at BC000h-BFFFFh,

7 Set for 640x200 16color mode, clear for all other (16color?) modes.

3DEh (R/W): AT&T Mode Register (CT82c426 only)

bit 0 AT&T Mode. Only effective if 3D4h index D8h bit 5 is set.

If clear text modes are displayed as 16line characters and graphics

modes are displayed 200 line scandoubled resolution.

If set text modes are displayed with 16line characters and graphics

modes are displayed as true 400 line modes.

3 Page Select. If set display memory is in the 16KB starting from

BC000h, if clear in the 16KB starting at B8000h. If there is less

than 32KB of video memory this has no effect.

6 Enable Underline. If set bit 0 of the attribute byte selects

underline (as in the MDA), if clear it selects blue ForeGround.

Note: this register is only accessible if 3D4h index D8h bit 5 is set.

3DFh (W): (AGA - Plantronics)

bit 3 132column monochrome text mode

4 132column color text mode (3D8h bit 0 must be set)

5 Set emulation mode in lieu of DIP switch

6 Set monochrome mode in lieu of DIP switch

7 Set color mode in lieu of DIP switch

Video Modes:

00h T 40 25 2 (8x8)

01h T 40 25 2 (8x8)

02h T 80 25 16 (8x8)

03h T 80 25 16 (8x8)

04h G 320 200 4

05h G 320 200 4

06h G 640 200 2