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INVITED KEYNOTES & PLENARY TALKS
- S. Dutta, ``The Changing Landscape of IP-Based Multimedia SoC Design, Invited plenary talk at the International Symposium on Consumer Electronics, Algarve (Portugal), April 2008.
- S. Dutta, ``Recent Trends in the Design of Video Signal Processing IPs and Multimedia SoCs, Invited keynote at the International Conference on Signal Processing and Multimedia, Barcelona (Spain), July 2007.
- S. Dutta, ``Designing Multiprocessor SoCs for Multimedia, Invited talk at National University of Singapore, Singapore, July 2006.
- S. Dutta, ``Recent Trends in the Design of Multi-Million-Gate Multimedia SoCs, Invited Computer Engineering Research Seminar at Princeton University, Princeton, New Jersey (USA), September 2005.
- S. Dutta, ``Design of Multimillion-Gate Multimedia SoCs: Where do we stand?, Keynote talk at the
3rd Workshop on Embedded Systems for Real-Time Multimedia, New York Metropolitan (USA), September 2005.
- S. Dutta, ``Trends in Platform Based Multiprocessor SoC Designs, Keynote talk at the
Application-Specific Multiprocessor SoC, Relais de Margaux (France), July 2005.
- S. Dutta, ``Platform Based Multiprocessor Designs, Invited tutorial at the 42nd Design Automation Conference, Anaheim (USA), June 2005.
- S. Dutta, ``Standard Architecture and Design for Video Engines,'' Invited talk at the Philips
World-Wide Technology Conference, Barcelona (Spain), November 2004.
- S. Dutta,
``Recent Trends in Multi-Million-Gate Multimedia SoC Designs,
Keynote talk at the IP Based SoC Design Workshop, Grenoble
(France), November 2003.
- S. Dutta,
``Future Systems Design,
Invited panel at the 16th Symposium on Integrated
Circuits and Systems Design (Chip in Sampa), on The Convergence Of Technology,
Design, And Tools'', Sao Paulo (Brazil), September 2003.
- S. Dutta,
``Architecture and Implementation of
Multi-processor SOCs for Advanced Set-Top Box and Digital TV Systems,
Invited talk at the
16th Symposium on Integrated Circuits and
Systems Design (Chip in Sampa), Sao Paulo (Brazil), September 2003.
- S. Dutta,
``Architecture, Design, Verification, and Validation
of Multi-Processor SOCs for DTV, ASTB, and Media Processing
Applications,
Invited tutorial at the International Symposium on Industrial Electronics
(ISIE), L'Aquila (Italy), July 2002.
- S. Dutta,
``Architecture and Implementation of Application-Specific Multi-processor
SOCs for Digital TV (DTV) and Media-Processing Applications,
Invited talk at the Application-Specific Multi-Processor
SoC, Aix-lex`s-Baines (France), July 2001.
- S. Dutta,
``Architecture, Design, and Verification of an 18 Million Transistor Digital Television and Media Processor Chip,
Invited talk at the
International Workshop - Power and Timing Modeling,
Optimization and Simulation (PATMOS), Hannover (Germany), September 2000.
- S. Dutta, ``Architecture and Design of NX-2700: A Programmable
Single-Chip HDTV All-Format-Decode-&-Display Processor, Invited panel at the 37th Design Automation Conference, Panel on bleeding-edge chip design, Los Angeles (California, USA), June 2000.
- S. Dutta, ``Verification & Validation of TM2700: A Programmable
Single-Chip HDTV All-Format-Decode-&-Display Processor, Invited talk at the Computer-Aided
Network Design (CANDE), Arizona
(USA), May 1999.
JOURNAL/BOOK PUBLICATIONS
- S. Dutta, et al, ``MPSoCs for Video,'' Invited book chapter Multiprocessor Systems on Chips, San
Francisco, CA:Morgan Kaufmann, 2005.
- S. Dutta, et al, ``Architecture and Implementation of
VIPER: A Multiprocessor SOC for ASTB and DTV Systems,''
invited paper
IEEE Design & Test - Special Issue on Application-Specific
Multi-Processor System on Chip, September/October 2001.
- S. Dutta, ``Architecture and Design of NX-2700: a Programmable Single-Chip HDTV All-Format-Decode-and-Display Processor,''
IEEE Transactions on VLSI Systems, April, 2000.
- S. Dutta, et al, ``Architecture and Design of a
Talisman-Compatible Multimedia Processor,''
IEEE Transactions on Circuits and
Systems for Video Technology, June 1999.
- S. Dutta and W. Wolf, ``A Circuit-Driven Design Methodology for Video Signal Processing
Datapath Elements,'' IEEE Transactions on VLSI Systems, June
1999.
- S. Dutta, K. O'Connor, W. Wolf, and A. Wolfe, ``A Design Study of a 0.25 Micron Video
Signal Processor,'' IEEE Transactions on Circuits and Systems for Video Technology,
August, 1998.
- S. Dutta, W. Wolf, and A. Wolfe, ``A Methodology to Evaluate Memory Architecture
Design Trade-Offs for Video Signal Processors,''
IEEE Transactions on Circuits and
Systems for Video Technology, February 1997.
- S. Dutta and W. Wolf, ``A Flexible Parallel Architecture Adapted to
Block-Matching Motion-Estimation
Algorithms,'' IEEE Transactions on Circuits and
Systems for Video Technology, February, 1996.
- S. Dutta and W. Wolf, ``Asymptotic Limits of Video Signal Processing
Architectures,'' IEEE Transactions on Circuits and
Systems for Video Technology, vol. 5, no. 6, December 1995.
- S. Dutta, M. Shetti, and S. Lusky, ``A Comprehensive Analytical Model for
CMOS Inverters,''
IEEE Journal of Solid-State Circuits,
vol. 30, no. 8, August 1995.
CONFERENCE/WORKSHOP/MAGAZINE PUBLICATIONS
- B. Raman, S. Chakraborty, W. Ooi, and S. Dutta, ``Reducing Data-
Memory Footprint of Multimedia Applications by Delay Redistribution,'' Design Automation Conference (DAC), June 2007.
- S. Rathnam, H. Antwerpen, S. Dutta. et al, ``Design of Television Media Processor,'' Philips
DSP Conference, November 2003.
- S. Dutta, ``Design Verification of an 18-Million-Transistor Digital
Television and Media Processor Chip,'' IEEE International Conference
on Electronics, Circuits, and Systems (ICECS), September 2001.
- S. Dutta, ``Architecture, Design, and Verification of an 18 Million Transistor Digital Television
and Media Processor Chip,'' International Workshop Power and Timing Modeling, Optimization
and Simulation (PATMOS), September 2000.
- S. Dutta, D. Singh, E. Abu-Ghoush, and V. Mehra,
``Architecture and Implementation of a High-Definition Video
Co-Processor for Digital Television Applications,''
13th International Conference on VLSI Design, January 2000.
- S. Dutta, D. Singh, and V. Mehra,
``Architecture and Implementation of a Single-Chip Programmable
Digital Television and Media Processor,''
IEEE Workshop on Signal Processing Systems (SiPS), October 1999.
- A. Wolfe, W. Wolf, S. Dutta, J. Fritts,
``Design Methodology for Programmable Video Signal Processors,''
IS&T/SPIE's International Conference on Multimedia Processing
& Applications, Electronic Imaging (EI) '97,
February 1997.
- A. Wolfe, J. Fritts, S. Dutta, et. al.,
``Datapath Design for a VLIW Video Signal Processor,''
Third International Symposium on High-Performance Computer Architecture,
January 1997.
- S. Dutta, K. O'Connor, W. Wolf, and A. Wolfe,
``VLSI Issues for VLIW Video Signal Processor,''
IEEE Workshop on VLSI Signal Processing, October 1996.
- S. Dutta, K. O'Connor, and A. Wolfe, ``High Performance Crossbar Interconnect for
a VLIW Video Signal Processor,'' Proc. of the 1996 Ninth Annual
IEEE International ASIC Conference, September, 1996.
- S. Dutta and W. Wolf, ``Processing Element Design for Programmable VLSI Video Signal Processors,''IEEE Workshop on VLSI Signal Processing, October 1995.
- S. Dutta, W. Wolf, and A. Wolfe, ``VLSI Issues in Memory-System Design
for Video Signal Processors,'' IEEE International Conference on Computer Design (ICCD),
October 1995.
- S. Dutta and W. Wolf, ``Asymptotic Limits of Video Signal Processing
Architectures,'' IEEE International Conference on Computer Design (ICCD),
October 1994.
- S. Dutta, S. Nag, and K. Roy, ``ASAP: A Transistor Sizing Tool for Speed, Area, and Power Optimization of Static CMOS Circuits,'' IEEE International Symposium on Circuits and Systems (ISCAS), 1994.
- K.Roy, S. Nag, and S. Dutta, ``Channel Architecture Optimization for Performance and Routability of
Row-Based FPGAs,''
IEEE International Conference on Computer Design (ICCD), October 1993.
- H. Chen, S. Agarwala, S. Dutta, et.al., ``Circuit Optimization Techniques in DROID,''
International Symposium on VLSI Technology, Systems, and Applications, May 1991.
- D. Holberg, S. Dutta, and L. Pillage, ``Piecewise Quadratic Transistor Models for Bipolar and MOS Logic
Stage Delay Evaluation,'' International Conference on Computer-Aided Design (ICCAD),
November 1990.
- S. Dutta and L. Pillage, ``Calculating the Moments in AWE with Linear Complexity,''
Techcon'90, October 1990.
- L. Pillage and S. Dutta, ``A Path Tracing Algorithm for Asymptotic Waveform Evaluation of Lumped
RLC Circuit Delay Models,'' ACM Workshop on Timing Issues in the Specification and
Synthesis of Digital Systems (Tau '90), August 1990.
- H. Chen and S. Dutta, ``A Timing Model for Static CMOS Gates,''
International Conference on Computer-Aided Design (ICCAD), November 1989.
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Santanu Dutta
Thu Oct 7 11:18:22 PDT 1999