The aims of this project are:

• Define an architecture for an embedded RISC  microprocessor.
• A scaleable acrhitecture from 16 bit to 32 and even 8 or 64 bit.
• Style of architecture somewhere between a PIC(MicroChip) and a SH(Hitachi).
• Implement the processor in a HDL form (VHDL or Verilog) than can be synthesised to FPGA or a standard cell ASIC.
• Use of standard PROM and SRAM for program and data memories (not dual port or synchronous).
• Simple single clock cycle instructions where possible.
• Interrupts if possible
• 16 bit instructions (as SH or ARM-Thumb) for all data widths.
• Support tools such as an instruction set simulator and assembler are required to exersize the design and allow simple applications to be written.

These have led to a number of design descisions:

• Separate instruction and data memory buses.
• Simplify design at expence of size of core/code size/power etc.
• Reduced arithmetic operators (no multiply yet).
• Load store architecture with lots of registers (say 16).
• Use one of the general purpose registers as the stack pointer.