CPU Roadmap
| CPU | Release | Speed | Specs | |
|---|---|---|---|---|
| AMD | K6-III | 22 Feb 1999 | 400 450 |
K6-2 + Integrated 256KBytes L2 Cache Remaps 2.0x multiplier to 6.0x Die Size: 119 mm^2 |
| Athlon (K7) | 23 Jun 1999 | 500 550 600 |
L1 Cache: 128KB (64+64) 512KB to 8MB In cartridge L2 Cache Fab. Process: 0.25 micron Die Size: 184 mm^2 Transistor: 22 milioni Scalable Multiprocessing Architecture Multimedia extension: MMX, Enhanced 3DNow! CPU interface: Slot A Alpha EV6 200 MHz system bus (scalable beyond 400 MHz) |
|
| Athlon | 9 Aug 1999 | 650 | ||
| Athlon | 4 Oct 1999 | 700 | ||
| Athlon | 29 Nov 1999 | 750 | L1 Cache: 128KB (64+64) Die Size: 102 mm^2 Fab. Process: 0.18 micron $783US |
|
| K6-III | 13 Dec 1999 | 500 | ||
| K6-2 | Q4 1999 | 533 | ||
| K6-2+ | 1Q 2000 | ? | 0.18-micron version of the K6-2 with 128K on-die L2 cache Supports "Gemini" technology : enhanced mobile features, lower power consumption reducing operating voltage and processor clock speed (200 MHz as the speed for the mode optimized for the longest battery life). Additional pins will be required to control the programmable voltage regulator |
|
| K6-III+ | ? | ? | 0.18-micron, 256K on-die L2 cache Supports "Gemini" technology |
|
| Athlon | 06 Jan 2000 | 800 | Fab. Process: 0.18 micron | |
| Athlon | 11 Feb 2000 | 850 | ||
| Athlon | 6 Mar 2000 | 900 950 1000 |
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| Athlon (Thunderbird) | 5 Jun 2000 | 750 800 850 900 950 1000 |
Slot A and Socket A 256 KB on-die L2 cache Fab. Process: 0.18 micron aluminum (Fab 25), copper (Fab 30) $319, $359, $507, $589, $759, $990 |
|
| Duron | 19 Jun 2000 | 600 650 700 |
Socket A 64K on-die L2 cache $112, $154, $192 aka: Athlon Spitfire |
|
| Duron | 5 Sep 2000 | 750 | Socket A 64K on-die L2 cache $181 |
|
| Athlon (Thunderbird) | Q4 2000 | 1100 1133 1200 1333 |
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| Athlon (Mustang) | Q4 2000 | 1400 | Slot A and Socket A. 512KB - 2MB on-die L2 cache Enhanced core, and mobile features. 266 MHz Bus copper interconnects 16-way associative L2 cache |
|
| Palomino | End 2000 | ? | Socket A 256K on-die L2 cache Available in both a desktop and mobile version AKA: Corvette |
|
| Morgan | End 2000 | 900 | Value PC 64-Kbyte on-chip cache Available in both a desktop and mobile version AKA: Camaro |
|
| Sledgehammer | End 2001 | ? | x86-64 instruction set Server market Fab. Process: 0.18 - 0.13 micron First AMD processor to use Lightning Fast Transfer I/O bus AKA: K8 |
|
| Clawhammer | 2002 | ? | x86-64 instruction set Desktop market Fab. Process: 0.18 - 0.13 micron AKA: K8 |
|
| Cyrix | Mxi | Apr 1999 | 333 - 400 |
Super 7, 11-stage deep-pipeline, 3DNow!, (Cayenne core) |
| MediaPC | Jun 1999 | 233-300 | Super 7, integrates graphics an peripheral logic (Cayenne core) | |
| MII | ? | PR400 PR433 PR466 |
Fab. Process: 0.18 micron | |
| MII | Nov 1999 | PR366 PR400 PR433 |
Fab. Process: 0.25 micron | |
| Joshua | Mar 2000 | ? | Multimedia extension: MMX (2 units), 3DNow! on chip 256 KB level 2 cache CPU interface: Socket 370 133MHz Aimed at the low end of the market Jalapeno core? (ex Jedi, Gobi, MII+) |
|
| M3 (Mojave) | Mid 2000 ?? | 600-800 | Jalapeno core: on chip 256 KB level 2 cache, 16+16 KB level 1 cache, 0.18-micron, 2 integer units, 2 FP/MMX/3DNow! units. DRAM and 3-D graphics controller (Consigned to oblivion by VIA) |
|
| Elbrus | E2k | 2000 | 1200 | VLIW Instruction Set Architecture 16KB 2 Clock Level 1 Cache 256KB 8 Clock Level 2 Cache (On chip) Low ~35W Power Consumption 126 mm2 Die Size (0.18 micron) Power Consumption: 35W SPECint95: 135 SPECfp95: 350 |
| IDT | Winchip 2 | Nov 1998 | 200 225 240 266 300 |
L1 Cache: 32+32 KB Fab. Process: 0.25 micron Multimedia extensions: MMX, 3DNow! CPU Interface: Super 7 'Slightly faster in integer [than Winchip], but twice as fast in fpu.' (JC) |
| Winchip 3 | 1H 1999 | 266 | Integrated 128K L2 Cache | |
| Winchip 4 | 2H 1999 | 400-500 | 0.25 micron 2.5V, Super7 | |
| Winchip 5 | Q2 2000 | 400-700 | 0.18 micron PGA370 133 MHz 256K L1 Cache |
|
| Winchip 4 | 1H 2000 | 500-700 | 0.18 micron 1.8V, 'Different slot' Integrated 128K L2 Cache (VIA Samuel) |
|
| Intel | Celeron | Jan 99 | 366 400 |
16KB+16KB L1 Cache 128KB integrated L2 Cache Fab. Process: 0.25 micron Multimedia extension: MMX CPU interface: Socket 370 |
| Pentium III | 26 Feb 1999 | 450 500 |
16KB+16KB L1 Cache 512K Level Two Cache Fab. Process: 0.25 micron Multimedia extension: Streaming SIMD Extension CPU interface: Slot1 100MHz Embedded individual serial number and thermal noise random number generator |
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| Pentium III Xeon | 17 Mar 1999 | 500 | Fab. Process: 0.25 micron Multimedia extension: Streaming SIMD Extension CPU interface: Slot2 AKA: Tanner [server market] |
|
| Celeron | 26 Apr 1999 | 466 | $170 in 1,000 unit quantities | |
| Pentium III | 16 May 1999 | 550 | ||
| Celeron | 28 Jul 1999 | 500 | ||
| Pentium III | 28 Jul 1999 | 600 | ||
| Pentium III B | 27 Sep 1999 | 533 600 |
Fab. Process: 0.25 micron Multimedia extension: Streaming SIMD Extension CPU interface: Slot1 133MHz |
|
| Pentium III E (Coppermine) | 25 Oct 1999 | 600 650 700 |
Fab. Process: 0.18 micron 256KB integrated full speed L2 Cache Multimedia extension: Streaming SIMD Extension CPU interface: Slot 1 100 MHz 36-bit memory addressing 700 : $785/$770 10/100 pieces 650 : $610/$595 10/100 piece [mainstream market] |
|
| Pentium III E | 25 Oct 1999 | 500 550 |
Coppermine Core CPU interface: Socket 370 (FC-PGA370) 100 MHz 550 : $385 10 pieces 500 : $255 10 pieces |
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| Pentium III Xeon | 25 Oct 1999 | 667 733 |
16KB+16KB L1 Cache 256K (1MB??) integrated L2 Cache Fab. Process: 0.18 micron Multimedia extension: MMX, SSE CPU interface: Slot2 133MHz 733 : $865 10 pieces 667 : $688 10 pieces Coppermine Core AKA: Cascades [server market] |
|
| Pentium III EB (Coppermine) | 25 Oct 1999 | 533 667 733 |
Fab. Process: 0.18 micron 256KB integrated full speed L2 Cache Multimedia extension: Streaming SIMD Extension CPU interface: Slot 1 133MHz 36-bit memory addressing 733 : $810/$790 10/100 pieces 667 : $630/$620 10/100 pieces [mainstream market] |
|
| Pentium III | 20 Dec 1999 | 750 800 |
$803, $851 | |
| Celeron | Q1 2000 | 533 566 |
$170 | |
| Pentium III | 20 Mar 2000? | 850 866 |
$775 | |
| Celeron | 29 Mar 2000 | 600 | $170 | |
| Pentium III | 8 Mar 2000 | 1000 | ||
| Pentium III | 24 May 2000 | 933 | ||
| Celeron | 19 Jun 2000 | 633 667 |
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| Pentium III | 31 Jul 2000 | 1100 | ||
| Celeron | Q3 2000 | 700 | ||
| Itanium | Oct 2000 | 600-800 | IA-64, 0.18 micron, three-level on chip cache, Slot M, 8 single-precision floating point operations or 4 'extended-precision' floating point operations in a single cycle. up to 4MB of secondary cache memory. 6 Gflops of single-precision floating-point and 3 Gflops double precision. [Aka: Merced] |
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| McKinley | 2001 (2003?) | 900 | IA-64, 0.13 micron P858 aluminium technology. |
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| Pentium 4 Tualatin | 2001 | ? | 0.13 micron aimed at the $1,000-$1,500 mid-range PC market 512KB of integrated cache 200-MHz system bus |
|
| Pentium 4 | Q4 2000 | 1000 1400 |
IA-32, 0.18 micron, >1MB integrate level 2 cache, desktop PC Winstone98: 50, SpecInt95:43 at 1100MHz (Source: Intel) CPU interface: 423-pin socket ? Additional SIMD instructions. "Estimated to underperform the P3 or Athlon by more than 20 percent" [AKA Willamette] |
|
| Timna | Q1 2000 | 600 666 |
system on a chip device built-in graphics chip and a memory controller 128K level two cache on the die 370 pin socket |
|
| Tulloch ?? | Q2 2001 | 1600 1700 |
IA-32 CPU interface: 479-pin socket single/dual Rambus channel |
|
| Pentium 4 Northwood ? | Q3 2001 | 2000 | 0.13 micron CPU interface: mPGA478 |
|
| Madison | 2002 | ? | IA-64 copper interconnect technology |
|
| Northwood | ? | 3000 | IA-64, 0.13 micron | |
| Deerfield | 2003 | ? | IA-64, mid-range servers and workstations The first IA-64 chip aimed at the consumer market |
|
| Rise | mP6 II | Q1 1999 | 300 | 256kB on-chip L2 0.25 micron |
| Tiger | Q3 1999 | 1.8 volt core, and will come supporting PC-100, PC-133 and PC-266 Socket 370 |
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| mP6 II | Q4 1999 | ? | 0.18-micron | |
| mP6 | Q4 1998 | 166 190 (P233) 200 (P266) |
16KB of on-chip L1 cache, 6-stage pipelined CPU, three-way superscalar Integer and MMX, pipelined floating-point unit, Super7, 0.25-micron, 'Basic PC'/notebook market |
|
| ST | STPC | 26 Oct 1998 | 66 | fifth-generation x86 processor, five-stage pipeline, a parallel-processing integral floating-point unit, 8-Kbyte unified level-one cache, graphics chipset, TFT flat-panel display controller, PCMCIA card interface, local system bus, a PS/2 mouse controller, two serial ports, universal parallel port, Costing less than $40, QNX support, 'Embedded systems' |
| Transmeta | Crusoe TM3120 | 19 Jan 2000 | 400 | - VLIW processor and x86 Code Morphing - Processor core operates at 333, 366, and 400 MHz - Integrated 64K-byte L1 instruction cache, 32K-byte L1 data cache - Integrated northbridge core logic features facilitate compact system designs - SDR SDRAM memory controller with 66-133 MHz, 3.3V interface - PCI bus controller (PCI 2.1 compliant) with 33 MHz, 3.3V interface - Advanced power management features and very-low power operation extend mobile battery life - Full System Management Mode (SMM) support - Compact 474-pin ceramic BGA package |
| Crusoe TM5400 | 2H 2000 | 700 | - VLIW processor and x86 Code Morphing - Processor core operates at 500-700 MHz - Integrated 64K-byte L1 instruction cache, 64K-byte L1 data cache - 256K-byte L2 write-back cache - Integrated northbridge core logic features facilitate compact system designs - DDR SDRAM memory controller with 100-133 MHz, 2.5V interface - SDR SDRAM memory controller with 66-133 MHz, 3.3V interface - PCI bus controller (PCI 2.1 compliant) with 33 MHz, 3.3V interface - LongRun TM advanced power management - 1-2 W @ 500-700 MHz, 1.2-1.6V running typical multimedia applications - 30 mW in deep sleep - Full System Management Mode (SMM) support - Compact 474-pin ceramic BGA package |
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| Crusoe TM5600 | 2H 2000 | 700 | - VLIW processor and x86 Code Morphing - Integrated 656-Kbytes on-chip cache - Compact 474-pin ceramic BGA package |
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| Crusoe TM5800 | 2H 2001 | 1000 | VLIW processor and x86 Code Morphing Processor core operates up to 1 GHz 128K-byte L1 cache 512KB-1MB L2 write-back cache Integrated Northbridge & AGP DDR SDRAM memory controller @ 200 MHz 0.13 micron process "standard 360-pin package" |
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| Astro | 2002 | 1400 | VLIW processor and x86 Code Morphing Processor core operates up to 1.4 GHz 128K-byte L1 cache 2MB L2 write-back cache Integrated Northbridge & AGP 0.13 micron process 0.5 W power consumption |
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© 1997-1999 Roan Soldaini.