Junaid Omar

720 SE 125th Ave, Vancouver, WA 98683

junaid_omar@hotmail.com

Profile:  A seasoned computer engineer with broad experience in EDA software design as well as ASIC design, verification and physical back-end design. Demonstrated skill in meeting tight deadlines and accomplishing successful tapeouts of multiple chips.

Education:

The University of Texas at Austin, Austin, TX

Master of Science in Electrical Engineering (1994)

University of Engineering & Technology, Lahore, Pakistan

Bachelor of Science in Electrical Engineering (Honors) (1992)

 

Work Experience:

 

 

2007-present             Sr. MTS  Design Engineer , Vitesse, Lake Oswego, OR

·       Participated in the verification effort for the VSC34x ASIC with 6G serdes and signal recovery. Verified the switch core, register map and I2C interface using Tcl and Verilog

·       Led the verification effort for VSC3316, a 16x16 11Gbs ASIC. Developed the verfication environment and testbenches in SystemVerilog

·       Led the back-end  effort for the digital portion of the VSC3316 chip. Did synthesis and place&route using Magma BlastRtl and BlastFusion. Did Power anlaysis using BlastRail.

 

 

 

2003-2006      Physical Design Engineer, Analog Devices, Vancouver, WA

·         Participated in the successful tapeout of multiple ASICs with single or dual Blackfin DSP cores, using 0.13u TSMC 5 layer metal process. Did library prep., synthesis, P&R, timing closure etc. Delivered DRC/LVS-clean drop-in layout for the digital portion of the chip.

·         Wrote PERL and AWK scripts to provide glue logic between various tools in the flow and to filter information out of timing reports

 

2000-2003            Phys. Des./Verif. Engineer, Network Elements , Beaverton, OR

·         Worked on the physical place & route effort using Synopsys Astro, Jupiter XT , Apollo and Hercules tools. Quickly came up to speed on NEI’s  COT (customer-owned tooling) flow. This involved  participation  in all aspects of the COT flow from library prep. for Milkyway, tech file development, floorplanning, muli-domain power mesh , place & route , multi-clock CTS, timing closure, ECOs  and DRC/LVS.  Successfully taped out the digital portion of two mixed-signal chips using Synopsys Astro/Jupiter/Hercules family of tools. The first was a smaller test chip and the second was a 500K  gate flip-chip with 10 Gig CMOS SERDES.

·         Worked on verification of "Lithium", a multi-protocol processor for 10G Ethernet. Developed the verification infrastructure in C++. Verified  the SONET/SDH and OTN  (Optical Wrapper) blocks. . Used VCS directC PLI interface to  connect  the SPI4 interface to RTL.  Developed numerous directed and system level tests

1999-2000    Design Engineer, Micron Technology, Hillsboro, OR

·        Participated in the RTL design of a graphical resizer engine ASIC. Implemented the cubic and non-linear resizers for graphics and text resizing respectively. Participated in the development of the triangle engine reference model using Verilog PLI and C .


1997-1999             Development Engineer, Mentor Graphics , Wilsonville, OR

·        Developed software for Monet, a behavioral synthesis and architecture exploration tool, in  a large team of 15 development and QA engineers working on a project with 1+ million lines of C++ code

·        Developed   Monet Verilog netlister from scratch. Maintained VHDL netlister.

 

 10/94 - 11/97            CAD Software Engineer, VLSI Technology , Tempe, AZ

·         Developed Verilog ,VHDL (VITAL) and Fastscan Model Generators for VLSI std. cell libraries using C++.

·         Developed a generic testbench suite and Verilog translation backend in C++ for the validation of above-mentioned  model generators.

Publications

·         “Optimal Approximations for the Newton-Raphson Division Algorithm”  by M. Schulte, J. Omar and E. Swartzlander -- SCAN 1993.

·         “Clock Skew and Delay Optimization for Reliable Buffered Clock Tree” by  S. Pullella, N. Menzes, J. Omar and L. Pillage -- ICCAD 1993

 

Computer Skills

·        CAD Software: Various Verilog and VHDL simulators (Modeltech, XL, VCS etc.), Verilog PLI, Direct C interface with VCS, Virsim,  Synopsys Design Compiler, Primetime,  Debussy, Astro,  Jupiter ,  Astro-Rail, Hercules, Magma Blast (RTL/Fusion/RTL) Family, SystemVerilog, Calibre

·        Programming: C++, C, System C,  Unix Shell scripting, Perl, awk etc.

·        Op. Systems: Strong UNIX background (Solaris, Linux etc.). Familiar with Windows ,

·        Misc. Software:  Various C++ compilers, profilers and debuggers  such as Gnu C compiler, Visual C++, Purify, Testcenter, template libraries, C++ STL lib,  GDB, Version control (RCS, ClearCase, CVS) ,  MS Office,  Emacs, Frame Maker

·        Training Courses : PrimeTime, Design Compiler, SystemC, Vera, SystemVerilog, Magma Blastfusion

 Work Status : U.S. Citizen